FPGA Implementation of Optimal Planar Systolic Arrays for Orthogonal Matrix Multiplication

نویسندگان

  • I. N. Tselepis
  • M. P. Bekakos
  • E. I. Milovanović
چکیده

In this paper, optimal 2-D Systolic Arrays for orthogonal matrix multiplication, as much as the corresponding hardware implementation is investigated. The selected platform is a FPGA (Field Programmable Gate Array) device since, in systolic computing, FPGAs can be used as dedicated computers in order to perform certain computations at very high frequencies. The description language used as an entry tool to model the hardware architecture is VHDL (Very High Speed Integrated Circuit Hardware Description Language).

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تاریخ انتشار 2007